1. Field of the Invention
The present invention relates to a digital-to-analog (D/A) converter, and more particularly to a D/A converter with low skew and glitches.
2. Description of the Related Art
In general, the D/A conversion is carried out by obtaining voltage values corresponding to sums of currents outputted from plural output sources controlled by switches that are turned on and off by a digital signal. At this time, the individual current sources have a different output current amount respectively based on a weighted value of a digital signal. For example, in a 4-bit D/A converter, currents outputted from current sources corresponding to the Least Significant Bit (LSB) and the Most Significant Bit (MSB) are at least two times or more different in amount. Upon switching the current sources having such differences in current amount, the larger current amounts the current sources produce, the slower their switching response speeds become. In order to solve the problem, the large current sources producing large current amounts should have a low internal resistance. Accordingly, as the number of current sources constituting a D/A converter increases, the turn-on resistance of switches switching on and off current sources for the MSBs should become lower.
FIG. 1 is a view for explaining an operation principle of a D/A converter.
The D/A converter shown in FIG. 1 is conceptually directed to a 4-bit D/A converter which has current cells 11, 12, 13, and 14, current switches 21, 22, 23, and 24, and a load resistor 30.
The current cells 11 to 14 each have a different current output amount based on weights thereof. For example, the current cells 11 to 14 output current amounts of 10 mA, 20 mA, 30 mA, and 40 mA, respectively. The current switches 21 to 24 respond to digital signals D1, D2, D3, and D4, and selectively enable the current cells 11 to 14. The enabled current switches 21 to 24 provides paths between the current cells 11 to 14 and a drive voltage VDD, to thereby apply certain output currents of the current cells 11 to 14 to the resistor 30. The currents applied to the resistor 30 are converted into certain voltage signals as outputs through the resistor 30. That is, the digital signals D1 to D4 are converted into an analog signal.
FIG. 2 is a block diagram for conceptually showing a conventional D/A converter.
The D/A converter shown in FIG. 2 is conceptually directed to a 4-bit D/A converter that has current cells 41, 42, 43, and 44, current switches 51, 52, 53, and 54, load resistors 61 and 62, and a latch 63.
The current cells 41 to 44 input a drive voltage VDD and output a certain current, respectively. The individual current cells 41 to 44 output a different current amount, respectively, based on their different weights.
The current switches 51 to 54 respond to digital signals D1 to D4 and selectively enable the current cells 41 to 44. In here, the current switches 51 to 54 respond to the digital signals D1 to D4, and then enable the current cells 41 to 44 to differentially output currents in the inverse and non-inverse manners. Accordingly, the currents generated from the current cells 41 to 44 flow through paths formed between the drive voltage VDD and the ground voltage GND all the time. As such, by keeping the current cells 41 to 44 turned on by the current switches 51 to 54 all the time, the chances of glitches occurring when a D/A converter performs D/A conversions are somewhat reduced, which is later described in detail.
FIG. 3A and FIG. 3B are views for conceptually explaining glitch occurrences due to the current switches shown in FIG. 1 and FIG. 2.
FIG. 3A is for explaining glitch occurrences when the current switches of FIG. 1, for example, a reference numeral 21, are turned off. FIG. 3A shows that, when a current path is cut off while a current source 11 applies a current to the ground voltage GND, a glitch occurs due to a phenomenon for recovering a voltage of node A up to the drive voltage VDD.
FIG. 3B is a view for conceptually showing the current switches of FIG. 2, for example, a reference numeral 51, in detail. As shown in FIG. 3B, the current switch 51 differentially operates by a digital signal D and its inverse digital signal /D. When the digital signal D is in logic “high”, a switch 51a electrically connects the current source 41 and the ground GND, and, when the digital signal D is in logic “low”, a switch 51b electrically connects the current source 41 and the ground GND. Accordingly, the current switch 51 shown in FIG. 3B reduces glitches greatly compared to the current switch of FIG. 3A.
FIG. 4 is a detailed circuit for showing a unit current switch and a unit current source for a D/A converter constructed based on the concept of the current switch shown in FIG. 3B.
The unit current switch shown in FIG. 4 has a first switching part 80 and a second switching part 90.
The first switching part 80 responds to the digital signal D and then outputs a current of the current source 70 to a first output terminal out1, and the second switching part 90 responds to the inverse digital signal /D and outputs the current of the current source 70 to a second output terminal out2. Accordingly, the first and second switching parts 80 and 90 alternately operate so as to output the current of the current source 70 to the first and second output terminals out 1 and out 2.
The first switching part 80 turns on a PMOS transistor 84 when the digital signal D is in logic “high”, so that the current of the current source 70 is outputted to the first output terminal out 1. Likewise, the second switching part 90 turns on a PMOS transistor 94 when the inverse digital signal /D is in logic “high”, so that the current of the current source 70 is outputted to the second output terminal out 2. At this time, NMOSs 81 and 82 of the first switching part 80 apply to the PMOS transistor 84 a voltage Vb applied to the gate of the NMOS 82, when the digital signal D is in logic “low”, in order for the current of the current source 70 not to be applied to the first output terminal out1 through the PMOS transistor 84. The NMOS transistor 81 is a switch turned on and off by the inverse digital signal /D, and the NMOS transistor 82 limits a source voltage of an NMOS transistor 81 to the gate voltage Vb, and applies the source voltage of an NMOS transistor 81 to the PMOS transistor 84. Therefore, a range of voltages applied to the PMOS transistor 84 becomes somewhat lowered by the voltage Vb, so that an absolute voltage value of glitch occurring at the first output terminal becomes lowered. The operations of the second switching part 90 are the same as those of the first switching part 80 except to drive the second output terminal out2 by the inverse digital signal /D, so the operations of the second switching part 90 will be omitted.
In the meantime, the unit current switch lowers its response speed as the current of the current source 70 increases in amount. In order to solve the problem of lowering its response speed, the internal resistance of a current switch providing a large current should be smaller than that of a current switch providing a small current. This means that, since the unit current switch corresponding to the MSB drives the largest current amount and the unit current switch corresponding to the LSB drives the smallest current amount when a D/A converter is constructed with the unit current switches as above, the D/A converter is designed to have the unit current switches each having a different turn-on resistance value depending upon current amounts respectively driven by the unit current switches. If the unit current switches for switching on and off the current sources have the same turn-on resistance regardless of the output current amounts of the current sources, the currents from the individual current sources reach the output terminal in different times, which causes the time skew.
FIG. 5A to FIG. 5D are cross-sectioned views for showing a process for forming a PMOS transistor, for example, a reference number 84 or 94, constituting a unit current switch when the unit current switch shown in FIG. 4 is applied to a 4-bit D/A converter.
FIG. 5A is a cross-sectioned view for showing a process for forming a PMOS transistor applied to the LSB, FIG. 5D is a cross-sectioned view for showing a process for forming a PMOS transistor applied to the MSB, and FIG. 5B and FIG. 5C are cross-sectioned views for showing a process for forming a PMOS transistor sequentially allocated to the LSB and the MSB, respectively.
As shown in FIGS. 5A, 5B, 5C, and 5D, a conventional MOS transistor has an oxide layer, for example, SiO2 layer, between its drain and source, and varies its turn-on resistance by increasing the width W of the SiO2 layer while keeping the length ‘L’ of the same constant. Such a process has an advantage of easily varying the turn-on resistance of the PMOS transistor with varying the width W of the SiO2 layer, but has a problem of increasing capacitance forming between the gate (not shown) and drain of a PMOS transistor. The capacitance formed between the gate and drain of the PMOS transistor increases turn-on and turn-off response time in response to a signal applied to the gate of the PMOS transistor, and causes a phenomenon that a signal applied to the gate of the PMOS transistor passes through to the drain of the same when the capacitance becomes large. That is, when such a PMOS transistor is employed in the unit current switch of a digital D/A converter, glitches occur at the output terminal of the D/A converter due to the pass-through phenomenon. Further, since individual PMOS transistors have different response times when the PMOS transistors have different capacitances, the time skew phenomenon occurs due to differences of the response times of the PMOS transistors. Accordingly, a D/A converter having such PMOS transistors causes errors to data values due to the response time differences as it performs D/A conversions at a high speed, and has a problem in performing D/A conversions since a high margin has to be assigned with respect to time interval of sampling in order to compensate for errors due to time skew.